The present invention is directed to integrated circuits and, more particularly, to using multi-bit clock gating cells to reduce power consumption by an integrated circuit.
Power consumption is critical in large integrated circuits (ICs) such as systems on chips (SOCs), which may have many million transistors. A widely used technique for reducing dynamic power consumption is to use clock gating cells to switch off the clock to portions of the IC while they are not required to operate. However, the clock gating cells themselves consume significant power and add to the complexity of the IC.
It would be advantageous to have a way of reducing the power consumption and complexity of the clock tree of an integrated circuit.